1. Technical Field
The present invention relates to a method of fabricating a semiconductor device, and particularly, to a method of forming a contact structure with a contact space, and a method of fabricating a semiconductor device using the same.
2. Discussion of the Related Art
In general, a semiconductor device includes an integrated circuit provided with such discrete devices as transistors, resistors and capacitors. The discrete devices can be electrically coupled to one another through contact holes passing through an interlayer dielectric layer.
As the integration degree of a semiconductor device increases, the size of the contact holes and the interval between the contact holes are gradually reduced. Therefore, a process margin for forming the contact holes and interconnections filling the contact holes is reduced. As a result, the yield rate of the semiconductor device suffers.
FIGS. 1A through 1C are cross-sectional views illustrating a method of forming conventional contact structures.
Referring to FIG. 1A, a device isolation layer 14 is formed in a predetermined region of a semiconductor substrate 10 to define a plurality of active regions 12. An interlayer dielectric layer 16 is formed on the semiconductor substrate 10 having the active regions 12. The interlayer dielectric layer 16 may include a silicon oxide layer. Subsequently, a mask pattern having openings, e.g., a photoresist pattern 19, is formed on the interlayer dielectric layer 16. The interlayer dielectric layer 16 is etched using the photoresist pattern 19 as an etching mask, thereby forming contact holes 18 for exposing the active regions 12. At this time, the etching may be performed through dry etching using an etching gas containing carbon and fluorine. In this case, sidewalls of the contact holes 18 can be formed not to have a profile vertical to the semiconductor substrate 10 but to have a profile tapered to the semiconductor substrate 10. This is because a polymer produced in the dry etching is adhered to the sidewalls of the contact holes 18. Moreover, when the contact holes 18 have a high aspect ratio, each of the contact holes 18 can have a profile, an upper portion of which has a width greater than a lower portion thereof.
Referring to FIG. 1B, a cleaning process is performed with respect to top surfaces of the active regions 12 exposed through the contact holes 18, using a cleaning solution. A solution containing a fluoric acid may be used as the cleaning solution 20. While performing the cleaning process, the cleaning solution 20 may etch the interlayer dielectric layer 16 adjacent to the contact holes 18. As described above, the distance between the contact holes 18 adjacent to each other is decreased due to the increase of the integration degree of the semiconductor device, and thus the width of the interlayer dielectric layer 16 between the contact holes 18 is reduced. Therefore, when, the interlayer dielectric layer 16 is over-etched, an opening O passing through the interlayer dielectric layer 16 between the contact holes 18 in a lateral direction may be formed.
Referring to FIG. 1C, the photoresist pattern 19 is removed, and a conductive layer is then deposited on an entire surface of the semiconductor substrate 10 having the contact holes 18. Subsequently, the conductive layer is planarized to expose a top surface of the interlayer dielectric layer 16, thereby forming conductive layer patterns 22 filling the contact holes 18. Although the respective conductive layer patterns 22 are electrically isolated by the interlayer dielectric layer 16 therebetween, a short circuit occurs through the opening O. Therefore, the reliability of the semiconductor device is degraded.
A method of fabricating a semiconductor device with another conventional contact structure has been disclosed in Korean Patent Laid-Open Publication No. 2005-0066369, entitled “Method of forming contact hole of semiconductor device.” According to Korean Patent Laid-Open Publication, before forming a contact hole for exposing a predetermined region of a semiconductor substrate, a trench is preliminarily formed in an interlayer dielectric layer. A spacer is formed on a sidewall of the trench, and the interlayer dielectric layer is then etched along the trench having the spacer, thereby forming the contact hole. However, since the contact hole has a lower area reduced by the width of the spacer, contact resistance between a contact plug filling the contact hole and the semiconductor substrate is increased.